View DS1481_312783.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS1481
PRELIMINARY
DS1481 1-Wire Bus Master with Overdrive
FEATURES
PIN ASSIGNMENT
VCC ENI O1/BSY1 O2/BSY2 D/CLK RES NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 I/O ENO I1 I2 NC NC GND
* Provides a synchronous interface to Dallas Semiconductor 1-wire devices
* Compatible with low power parallel ports * Can be cascaded with other DS1481's * Allows print spooler and other processes to run during
1-wire I/O
* Provides
high speed communcation with overdrive capable devices
14-PIN SOIC (150 MIL)
* Space saving 14-pin (150 mil), SOIC package
PIN DESCRIPTION
VCC ENI D/CLK RES O1/BSY1 O2/BSY2 GND I1 I2 I/O ENO NC - - - - - - - - - - - - Supply Enable In Data/Clock Reset Output 1/Busy 1 Output 2/Busy 2 Ground Input 1 Input 2 1-wire I/O Enable Out No Connect
DESCRIPTION
The DS1481 is a dedicated 1-wire timing generator. The device is normally used in conjunction with a parallel port controller to provide the necessary interface to the host processor. Busy signals allow the host processor to perform other tasks while 1-wire "time-slots" are completed. The DS1481 also saves the state of D/CLK and RES allowing print spoolers to operate without affecting 1-wire communication. DS1481 based devices can be cascaded. The first device's O1/BSY1 and O2/BSY2 connect to the PC printer port's BUSY and SELECT OUT signals (pins 11 and 13 respectively). The next DS1481 connects its O1/BSY1 and O2/BSY2 to the first device's I1 and I2 respectively. ENO of the first device connects to ENI of the second device. More DS1481's can be stacked in a similar manner. The last devices I1 and I2 connect to BUSY and SELECT of the attached printer. The DS1481's 3-volt operation insures compatibility with most low power parallel ports (i.e., portable computers).
021798 1/10
DS1481
OPERATION
One wire communication is executed in "time slots". The DS1481 generates either a read/write bit "time slot" or a reset on the I/O pin. The operation performed is determined by the states of the D/CLK and RES pins as follows: TIME SLOT Read 0, Read 1, Write 1 Write 0 1-wire Reset D/CLK logic high logic low logic high RES logic high (see Figure 4) logic high (see Figure 5) logic low (see Figure 6)
1-WIRE TIMING GENERATION
For all time slots, the DS1481 samples the I/O pin at tSO (see Figure 4). The DS1481 waits a minimun of 60 s from the start of the time slot and de-asserts O1/BSY1 and O2/BSY2. When a reset is requested, the DS1481 drives the I/O pin low for at least 480 s and then releases it. During a normal reset the I/O pin immediately begins to return high. If a 1-wire device is present on the I/O line it pulls I/O low after time T (15 s T 60 s) from the previous rising edge. The 1-wire device(s) holds the I/O line low for 4T and then releases it, allowing the I/O line to return high. This is the presence detect pulse. The I/O line must remain high (in its idle state) for at least 3T before the 1-wire device(s) is ready for further communication. To insure this idle high time is satisfied, the DS1481 does not release O1/BSY1 and O2/BSY2 for at least 960 s (measured from the 1st falling edge on the I/O pin). If after 480 s of low time the I/O line did not return high, either the I/O line has been shorted to ground or there is at least one 1-wire device connected to the I/O line which is issuing an alarm interrupt (see Figure 6). In this case the DS1481 waits for I/O to return high for an additional 3840 s (64 * 60). If time expires the I/O line is assumed to be shorted and the DS1481 releases O1/BSY1 and O2/BSY2. If the I/O line returns high, the DS1481 continues to monitor the presence detect portion of the reset (as described above) as for the non-interrupt case. Note that the 3T idle high time is still required after the presence detect ends.
After D/CLK and RES have been set, the time slot begins when ENI is driven to its active state. A falling edge on ENI causes the DS1481 to save the state of D/CLK and RES. If the time slot is a 1-wire reset the DS1481 will issue a busy signal by driving O1/BSY1 low and O2/BSY2 high. After 2 s O2/BSY2 is driven low. Both outputs will remain low until the communication on the I/O line is finished. A busy signal for a bit time slot differs from the reset busy signal only in that both O1/BSY1 and O2/BSY2 are driven low immediately. While the busy signal is asserted, the host processor is free to perform other tasks (including running the print spooler). When the time slot is complete, the DS1481 restores both O1/BSY1 and O2/BSY2 to the states of I1 and I2 (see Figure 1). When the host detects that one or both of the busy signals has returned high, it must query the result of the time slot. This is accomplished by driving D/CLK low. If the result of the time slot was low (Read 0, Write 0 or presence detect) the DS1481 drives both O1/BSY1 and O2/BSY2 low (this state is held until ENI returns high). Otherwise it propagates the states of I1 and I2. After the host reads the result of the time slot it must drive ENI to its inactive state (high). The DS1481 will then set O1/BSY1 and O2/BSY2 to the states of I1 and I2.
OVERDRIVE
The DS1481 also supports overdrive communication with overdrive capable 1-wire devices. When the DS1481 powers up it is in normal mode (i.e., OD = 0, Figure 1). To toggle to overdrive mode the host sets D/CLK and RES low and drives ENI low. The DS1481 toggles the OD bit to a logic high and returns the states of I1 and I2 on O1/BSY1 and O2/BSY2. Overdrive mode is cleared in the same way. When overdrive is turned off (OD = 0). O1/BSY1 and O2/BSY2 are driven low to report the state of the OD bit.
021798 2/10
DS1481
When OD = 1, communication with the 1-wire device is exactly as described in the operation section above. The actual 1-wire timing for both modes of operation is described in Figures 4, 5 and 6. Note that when toggling the OD bit there is no change on the I/O line.
If the DS1481 determines that it is the last device on the port it ignores the states of its I1 and I2 pins while ENI is low. It also leaves the ENO pin high to prevent sending line feed signals to the printer. This gives the last device the ability to control O1/BSY1 and O2/BSY2 without affecting stackability.
EPP/ECP TRANSPARENT MODE PRINTER COEXISTENCE
In order to coexist with parallel port printers, the DS1481 utilizes two input pins (I1 and I2) and two output pins (O1/BSY1 and O2/BSY2). When ENI is low these pins are used for transmitting data received on the I/O pin or for issuing an unmistakable busy signal. When ENI is inactive (high) O1/BSY1 and O2/BSY2 propagate the states of I1 and I2. If a printer is attached to a DS1481, I1 is connected to the printers BUSY signal (low only if printer is on line and busy), and I2 is connected to SELECT OUT (driven low if printer is off line), see Figure 2. If the attached printer is "powered up" and on line, the DS1481 uses SELECT OUT for communication regardless of the state of the printers BUSY signal. If the printer is off line its BUSY signal is inactive (high) and this line is used by the DS1481 for host communication. If the attached printer is powered off, both SELECT OUT and BUSY will be low. This prevents meaningful communication with the DS1481 because it is unable to de- assert its busy signal (O1/BSY1 and O2/BSY2 low) or return a high sample of the I/O pin. To solve this problem, the DS1481 uses the busy signal issued during a reset to detect the presence of another DS1481 based device attached behind it on the parallel port. If this busy signal is not detected by the DS1481, it assumes that it is the last DS1481 based device on the port. When the DS1481 first powers up it is in a transparent mode in which the three signal lines (auto line feed, busy and select) that pass through the part are directly connected by transmission gates. This allows bi-directional printers (or other parallel port peripherals) to communicate in either the EPP or ECP mode of the PC parallel port. The DS1481 pin sets connected are as follows: ENI O1/BSY1 O2/BSY2 ENO I1 I2
1-wire communication using the DS1481 is impossible in transparent mode. To toggle to normal mode four consecutive overdrive toggle commands must be issued. If this sequence has been issued and the ENI pin remains high for at least 10 ms the part will enter its normal mode of operation. Note that any other 1-wire time slot command issued during the sequence resets the sequence. The steps needed to return to transparent mode are as described above with the exception that no additional wait is required at the end of the four overdrive toggles to enter transparent mode. While in transparent mode if the DS1481 detects that the ENO pin has been held low for more than 10 ms it turns off the transmission gate connecting ENI and ENO. This guarantees the host will have the ability to take the DS1481 out of transparent mode and perform 1-wire I/O operations.
021798 3/10
DS1481
DS1481 FUNCTIONAL BLOCK DIAGRAM Figure 1
ENO ENI
LAST PART DETECTION D/CLK D Q 1-WIRE BUS 1-WIRE BUS MASTER
CLK Q RES D Q
I/O
CLK Q OD O1/BSY1
I1
O2/BSY2
I2
021798 4/10
DS1481
CONNECTION TO PC TYPE PARALLEL PORTS Figure 2
+5 VCC ENI O1/BSY1 O2/BSY2 D/CLK RES NC I/O ENO I1 I2 NC NC GND DS9100
P14 P11 P13 P2 P3
P14 P11 P13
TO HOST
P18
TO PRINTER OR ANOTHER PARALLEL PORT RESIDENT DEVICE
CONNECTION TO MICROCONTROLLERS Figure 3
DS80C320 +5 VCC ENI O1/BSY1 O2/BSY2 D/CLK RES NC I/O ENO I1 I2 NC NC GND DS9100
P1.0 P1.1 P1.2 P1.3
021798 5/10
DS1481
TIMING DIAGRAM: HOST INTERFACE Figure 4
ENI
VALID D/CLK
RES
VALID
O1/BSY1
O2/BSY2 tBLB READ 0 (I/O)
READ 1 (I/O)
WRITE 1 (I/O) tSIO tSIO = 8 s (TYPICAL), tBLB = 60 s (MINIMUM) tSIO = 2 s (MAXIMUM), tBLB = 6 s (MINIMUM) READ O, READ 1, WRITE 1 BIT TIME SLOTS (OD = 0) (OD = 1)
TIMING DIAGRAM: HOST INTERFACE Figure 5
ENI
D/CLK VALID VALID RES
O1/BSY1
O2/BSY2 tBLB
WRITE 0 (I/O)
tBLB = 60 s (MINIMUM) tBLB = 6 s (MINIMUM) WRITE 0 TIME SLOT
(OD = 0) (OD = 1)
021798 6/10
DS1481
TIMING DIAGRAM: HOST INTERFACE Figure 6
ENI
VALID D/CLK
RES VALID tBLR
O1/BSY1
O2/BSY2
RESET (I/O) tPDH = 2 s (TYPICAL) tBLR = 960 s (MINIMUM) tBLB = 96 s (MINIMUM) 1-WIRE RESET (OD = 0) (OD = 1)
TIMING DIAGRAM: HOST INTERFACE Figure 7
ENI
D/CLK VALID
RES
VALID
O1/BSY1
O2/BSY2 TOGGLE OVERDRIVE MODE
021798 7/10
DS1481
DETAILED PIN DESCRIPTION
PIN Vcc ENI O1/BSY1 I O TYPE DC supply voltage. Chip enable, driven low to begin 1-wire I/O. Driven low during time slot (to indicate a DS1481 busy condition). Set to state of I1 after time slot has finished. O1/BSY1 will go low after D/CLK goes low if sample of I/O communication was low. Returns to state of I1 when ENI goes back high (see Figure 1). Driven low during time slot (to indicate a DS1481 busy condition). Set to state of I2 after time slot has finished. O2/BSY2 will go low after D/CLK goes low if sample of I/O communication was low. Returns to state of I2 when ENI goes back high (see Figure 1). Data/Clock pin. Used to specify type of time slot before communication begins. After the time slot has been completed this pin is driven low in order to solicit the result of the time slot. Set low (before ENI is driven low) to specify that a reset pulse should be generated on the I/O pin. System ground. I I Can be connected to the O1/BSY1 of another DS1481. May also be connected to parallel port printer's BUSY signal. Internally pulled high via a weak resistor. Can be connected to the O2/BSY2 of another DS1481. Can also be connected to a parallel port printer SELECT OUT signal. Internally pulled high via a weak resistor. Set to ENI if not the last part on port. Open drain output with weak internal pull-up resistor. 1-wire I/O line. Bi-directional line with open drain output. DESCRIPTION
O2/BSY2
O
D/CLK
I
RES GND I1 I2
I
ENO I/O
O I/O
021798 8/10
DS1481
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to ground Operating temperature Storage temperature Soldering temperature -1.0V to +7.0V 0_C to 70_C -55_C to +125_C 260_C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VCC MIN 2.4 -0.3 2.7 5.0 TYP MAX VCC + 0.3 +0.8 5.5 UNITS V V V
(0_C to 40_C)
NOTES 1 1 1
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Output Leakage VOL @ ISINK = -2 mA I1 pull-up resistance I2 pull-up resistance ENI pull-up resistance ENO pull-up resistance D/CLK Pull-Up resistance RES Pull-Up resistance Active Current Available I/O Current ZI1 ZI2 ZENI ZENO ZDC ZR ICC II/O 40 50 50 50 50 50K 50K SYMBOL IIL ILO MIN -1 -1 TYP
(0_C to 40_C; 2.7 VCC 5.5)
MAX +1 +1 0.4 UNITS A A V K K K K NOTES 5
500
A mA
2 6
021798 9/10
DS1481
AC ELECTRICAL CHARACTERISTICS: HOST INTERFACE
PARAMETER Sample Time (for bit time slot, OD = 0) (for bit time slot, OD = 1) Recovery Time Data to Enable Hold Reset to Enable Hold Clock low time Clock low to O1, O2 valid BSY1, BSY2 low time (for bit time slot, OD = 0) (OD = 1) BSY1, BSY2 low time (for reset time slot, OD = 0) (OD = 1) SYMBOL tSIO tREC tDE tRE tCL tCOV tBLB 60 6 960 96 1 40 40 200 200 MIN TYP 8 2 s s ns ns ns s 3 MAX UNITS s NOTES
tBLR
s
4
NOTES:
1. All voltages are referenced to ground. 2. Measured with outputs open and I1, I2 high. 3. Minimum time required for 1-wire bit time slot. 4. Minimum time required for 1-wire reset time slot. 5. Only pins without pull-ups. 6. Overdrive mode only.
021798 10/10

▲Up To Search▲

Price & Availability of DS1481

	To Download DS1481 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .